1. Field of the Invention
The present invention relates to embedded silicon-straining material structures used to enhance semiconductor device performance.
2. Discussion of the Background
An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing power consumption in semiconductor devices. Planar transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are particularly well-suited for use in the high-density integrated circuits. As the size of MOSFETs and other devices decrease, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease. However, the benefits of simply making devices smaller (conventional scaling) are diminishing, and thus new material based innovations like embedded silicon-straining materials, such as embedded silicon germanium (eSiGe) and embedded silicon carbide (eSiC), that can boost performance have gained increased interest.
As micro-miniaturization of devices and circuits proceeds, there is an attendant need to increase the drive current of transistors by enhancing carrier mobility. Substrates based on “strained silicon” have attracted much interest as a semiconductor material that provides increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. In such a device, a very thin, tensely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition of SiGe buffer layer several microns thick, which SiGe buffer layer in turn is formed on a suitable crystalline substrate, e.g., a silicon wafer or a silicon-on-insulator (SOI) wafer. Strained silicon technology is based upon the tendency of silicon atoms, when deposited on a SiGe buffer layer, to align with the greater lattice constant (spacing) of SiGe atoms (relative to pure silicon).
As a consequence of the silicon atoms being deposited on a substrate (SiGe) comprised of atoms which are spaced further apart, they “stretch” to align with the underlying SiGe atoms, thereby “stretching” or tensely straining the deposited silicon layer. The electrons in such tensile strained silicon layers have greater mobility than in conventional, relaxed silicon layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow.
One method for applying compressive strain to the channels of p-channel MOSFET devices is known as an embedded SiGe (or eSiGe) technique. Such a technique applies uniaxial compressive strain to the channels of the PFET devices. In this technique, recesses are etched in the source and drains of the MOSFET devices, and are filled with selective epitaxial SiGe. Since the lattice constant of SiGe is different from that of silicon, mechanical strain is induced in the crystal layers to accommodate the lattice mismatch. The embedded geometry plus the compressive source/drain caused by the mismatch produces a relatively large uniaxial compressive channel strain. This produces a large enhancement in hole mobility.
Various parameters of an eSiGe structure can have an effect on the semiconductor device yield and performance. Thus, there is a need to provide accurate control of such parameters.